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=== [[C10 - Finite State Machine]] === | |||
#[[C10_-_Finite_State_Machine#Introducci.C3.B3n | Introducción]] | |||
#[[C10_-_Finite_State_Machine#Phase-Lock-Loop_.28PLL.29 | Phase-Lock-Loop]] | |||
##[[C10_-_Finite_State_Machine#Que_.C3.A9s.3F_C.C3.B3mo_funciona.3F | Que es? Como funciona?]] | |||
=== [[C11 - UART: The serial interface | <span style="color:black;">C11 - UART: The serial interface</span>]] === | |||
#[[C11_-_UART:_The_serial_interface#Synchronization | <span style="color:black;">Synchronization</span>]] | |||
#[[C11_-_UART:_The_serial_interface#Universal_Asynchronous_Receiver_Transmitter_.28UART.29 | Universal Asynchronous Receiver Transmitter (UART)]] | |||
=== [[C12 - Interrupts]] === | |||
#[[C12_-_Interrupts#Interrupt_Concepts | Interrupt Concepts]] | |||
#[[C12_-_Interrupts#Inter-thread_Communication_and_Synchronization | Inter-thread Comunication and Synchronization]] | |||
#[[C12_-_Interrupts#NVIC_on_the_ARM_Cortex-M_Processor | NVIC on the ARM Cortex-M Processor]] | |||
#[[C12_-_Interrupts#Edge-triggered_Interrupt | Edge-triggered Interrupt]] | |||
<math>V_{RELE}:</math> | |||
<math>V_{\text{RELE}}</math> | |||