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| | Embedded Systems<br/> |
| | [[C2 - Conceptos Fundamentales]]<br/> |
| | [[C4 - Lógica Digital]]<br/> |
| | [[C5 - Introducción a C]]<br/> |
| | [[C6 - Microcontroller Ports]]<br/> |
| | [[C7 - Design and Development Process]]<br> |
| | [[C10 - Finite State Machine]]<br> |
| | [[C11 - UART: The serial interface]]<br> |
| | [[C12 - Interrupts]]<br> |
| | <br/> |
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| Información Complementaria<br/> | | Información Complementaria<br/> |
| <br/> | | <br/> |
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Línea 15: |
| <br/> | | <br/> |
| [http://www.utm.mx/~fsantiag/Micros.htm http://www.utm.mx/~fsantiag/Micros.htm]<br/> | | [http://www.utm.mx/~fsantiag/Micros.htm http://www.utm.mx/~fsantiag/Micros.htm]<br/> |
| <br/>
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| [[File: arm_cortex_m.gif]]<br/>
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| Imagen Cortex-M ARM (CPU, Memoria, Perifericos, ...)<br/>
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| <br/>
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| *Arquitectura Harvard. ICode bus conecta con la ROM y System bus conecta con la RAM
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| *NVIC se encarga d elas interrupciones
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| *Algunos perifericos internos se conectan directamente con el procesador por el bus PPB
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| <br/> | | <br/> |
| Imagen CPU Cortex-M4 ARM<br/> | | Imagen CPU Cortex-M4 ARM<br/> |
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| *Decodificación | | *Decodificación |
| *Ejecución | | *Ejecución |
| Tipos de memoria:
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| *Memoria de Código
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| **Es en la que se almacena el programa
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| **Es no volátil
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| **Es la comunmente llamada ROM, y la tecnologia flash es una de las utilizadas para almacenar la ROM
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| ***La memoria flash se borra mediante impulsos eléctricos. Es una sucesora de la EEPROM
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| *Memoria de Datos
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| **Es la que almacena las variables del programa
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| **Es volátil
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| **Es la comunmente llamada RAM. La tecnologia que se utiliza para los microcontroladores es la SRAM
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| **También nos podemos encontrar con microcontroladores que ademas tienen memoria EEPROM para guardar datos cuando se corta la electricidad
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| Sistema de memoria:
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| *Arquitectura Von Neumann
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| **La Memoria de Código y la de Datos comparten el Bus hacia la CPU
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| *Arquitectura Harvard
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| **Hay un bus para la Memoria de Código y otro bus para la Memori de datos
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| <br/>
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| <br/>
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| <b>Tema 2</b><br/>
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| <br/>
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| <b>Memoria microcontroladores</b><br/>
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| <br/>
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| [http://es.wikipedia.org/wiki/Microcontrolador#Memoria Tipos de memoria]<br/>
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| [http://es.wikipedia.org/wiki/SRAM Memoria RAM (SRAM)]<br/>
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| [http://es.wikipedia.org/wiki/EEPROM Memoria ROM (EEPROM)]<br/>
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| [http://es.wikipedia.org/wiki/Memoria_flash Memoria ROM (Flash)]<br/>
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| <br/>
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| <b>Tipos de I/O</b><br/>
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| *Parallel - binary data are available simultaneously on a group of lines
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| *Serial - binary data are available one bit at a time on a single line
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| *Analog - data are encoded as an electrical voltage, current, or power
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| *Time - data are encoded as a period, frequency, pulse width, or phase shift
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| <br/>
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| <b>ISA (Instruction Set Architecture)</b><br/>
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| <br/>
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| <b>[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CHDBIBGJ.html Registros ARM ISA]</b><br/>
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| <br/>
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| [[File:registers.gif]]<br/>
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| <br/>
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| *R1...R12 - General Purpose Registers
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| **AAPCS (ARM Architecture Procedure Call Satandard) (parte de la ABI (ARM Application Binary Interface)) utiliza los registros R0, R1, R2 y R3 para pasar parámetros a las funciones de C
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| **Los parámetros que devuelven las funciones se colocan en el R0 según el AAPCS
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| **In this class, the SP will always be the main stack pointer (MSP), not the Process Stack Pointer (PSP).
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| *R13 - Stack Points (Almacena la dirección del elemento top de la pila)
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| *R14 - Link Register (Almacena la dirección devuelta por las subrutinas)
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| *R15 - Program Counter (Almacena la dirección de la siguiente instrucción a ejecutar)
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| Special Registers<br/>
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| *PSR - Process Status Register - Combina:
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| **APSR - Application Program Status Register
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| **IPSR - Interrupt Program Status Register
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| **EPSR - Execution Program Status Register
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| **Se puede consultar el registro PSR (que nos devuelve toda la información que contienen los tres registros), o consultar cada registro individulamente
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| **Los bits N, Z, V, C y Q nos dan información sobre el resultado de la anterior operación de la ALU
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| ***N resultado negativo
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| ***Z resultado es 0
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| ***V overflow signed numbers
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| ***C overflow unseigned numbers
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| ***Q indica que ha habido una saturacion
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| **El bit T siempre es 1 y nos indica que el procesador esta ejecutando instrucciones Thumb
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| **ISR_NUMBER indica el numero del tipo de excepcion actual del ISR
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| *PRIMASK (Exception Mask Registers) - Bit 0 of the special register PRIMASK is the interrupt mask bit. If this bit is 1, most interrupts and exceptions are not allowed. If the bit is 0, then interrupts are allowed.
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| *FAULTMASK (Exception Mask Registers) - Bit 0 of the special register FAULTMASK is the fault mask bit. If this bit is 1, all interrupts and faults are not allowed. If the bit is 0, then interrupts and faults are allowed. The nonmaskable interrupt (NMI) is not affected by these mask bits.
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| *BASEPRI (Exception Mask Registers) - The BASEPRI register defines the priority of the executing software. It prevents interrupts with lower or equal priority but allows higher priority interrupts. For example if BASEPRI equals 3, then requests with level 0, 1, and 2 can interrupt, while requests at levels 3 and higher will be postponed. A lower number means a higher priority interrupt. The details of interrupt processing will be presented in subsequent chapters.
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| <br/>
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| [[File:special_registers.gif]]<br/>
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| <br/>
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| Program Status Register del procesador ARM® Cortex-M<br/>
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| <br/>
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| <br/>
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| <b>Assembly language</b><br/>
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| <br/>
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| <br/>
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| Las instrucciones assembler tienen 4 campos separados por espacios o tabuladores:<br/>
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| Label - Opcode - Operand - Comment<br/>
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| FUNC - MOV - R0,#100 ; Pone 100 en R0<br/>
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| *Label field: Es opcional. Identifica la posicion en la memoria de la actual instrucción. Se debe elegir un único nombre para cada label.
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| *Opcode field: Es la isntrucción a ejecutar.
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| *Operand field: Especifica donde se encuentra el dato que ejecuta la instruccion. Las instrucciones Thumb tienen 1, 2, 3 o 4 operandos.
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| *Comment field: Son los comentarios y son opcionales. La forma correcta es explicar porque se pone esa instrucción, no explicar que hace.
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| <br/>
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| {|
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| !Label
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| !Opcode
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| !Operands
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| !Comment
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| |-
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| |Func
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| |MOV
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| |R0, #100
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| |; this sets R0 to 100
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| |-
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| |BX
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| |LR
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| |; this is a function return
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| |}
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| Las instrucciones se pueden clasificar en 4 categorias:
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| *Acceso a la memoria
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| *Instrucciones aritméticas y lógicas
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| *Instrucciones de control
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| *Resto de instrucciones
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| A fundamental issue in program development is the differentiation between data and address. When we put the number 1000 into Register R0, whether this is data or address depends on how the 1000 is used.
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| To run efficiently, we try to keep frequently accessed information in registers. However, we need to access memory to fetch parameters or save results. <b>The addressing mode is the format the instruction uses to specify the memory location to read or write data.</b>
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| <b>The addressing mode is associated more specifically with the operands, and a single instruction could exercise multiple addressing modes for each of the operands.</b>
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| When the import is obvious though, we will use the expression “the addressing mode of the instruction”, rather than “the addressing mode of an operand in an instruction". All instructions begin by fetching the machine instruction (op code and operand) pointed to by the PC. When extended with Thumb-2 technology, some machine instructions are 16 bits wide, while others are 32 bits.
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| <b>Some instructions operate completely within the processor and require no memory data fetches.</b> For example, the ADD R1,R2 instruction performs R1+R2 and stores the sum back into R1. If the data is found in the instruction itself, like MOV R0,#1, the instruction uses <b>immediate addressing mode</b>.
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| A register that contains the address or the location of the data is called a pointer or index register. <b>Indexed addressing mode</b> uses a register pointer to access memory. The addressing mode that uses the PC as the pointer is called <b>PC-relative addressing mode</b>. It is used for branching, for calling functions, and accessing constant data stored in ROM. The addressing mode is called PC relative because the machine code contains the address difference between where the program is now and the address to which the program will access. The MOV instruction will move data within the processor without accessing memory. The LDR instruction will read a 32-bit word from memory and place the data in a register. With PC-relative addressing, the assembler automatically calculates the correct PC offset.
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| Register. Most instructions operate on the registers. In general, data flows towards the op code (right to left). In other words, the register closest to the op code gets the result of the operation. In each of these instructions, the result goes into R2.
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| <br/> | | <br/> |
| Memory Map Layout<br/>
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| *ROM/Flash
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| *RAM
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| *I/O Ports
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| *Internal I/O<br/>
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| <br/> | | <br/> |
| | Recursos |
| | *https://www.smashwords.com/books/view/302372 - Libro en castellano de desarrollo en ARM M3 de Sergio R. Caprile |
| | *http://www.sase.com.ar/2012/files/2012/09/Pres_ARMando.pdf - Presentacion pdf resumen arm de Sergio R. Caprile |
| | *http://mymoviestorrent.com/e-books/90968-the-designers-guide-to-the-cortex-m-processor-family-a-tutorial-approach.html - The Designer's Guide to the Cortex-M Processor Family - A Tutorial Approach - |
| | *http://users.ece.utexas.edu/~valvano/embed/toc1.htm - Aprendizaje C para ARM de J.Valvano |
| | *http://www.forosdeelectronica.com/f24/empezar-microcontroladores-arm-55856/index2.html - Discusion sobre ARM. Interesante, hablan de placas de desarrollo y de las diferentes marcas que hacen ARM |
| | *https://www.youtube.com/user/valenciaupv/search?query=arm - Canal youtube de Universidad Politecnica Valencia |